In complementary metal oxide semiconductor (CMOS) technologies, process variations during manufacturing have a significant impact on circuit performance, such as timing. The effect of these variations worsens as minimum feature sizes scale down and as circuit complexity and die sizes increase. In many of today's integrated circuit (IC) design implementation flows, variability in devices and interconnects is modeled by timing analysis and optimization of a design at multiple process corners.
Generally speaking, timing analysis calculates circuit timing delays and ensures that those delays are within bounds as specified by user constraints. There are two major types of timing analyses, namely, static timing analysis and dynamic timing analysis. Static timing analysis basically calculates all of the individual delays associated with different portions of a circuit and then generates a report detailing the minimum and maximum delays associated with each possible path and whether those delays meet user constraints. On the other hand, dynamic timing analysis typically specifies an event that may occur sometime within a certain time period and then determines the timing along different paths of the circuit in response to the event. In other words, dynamic timing analysis is event-driven.
In conventional static timing analysis, models at various process corners have significant pessimism built into them. Generally speaking, pessimism in the current context refers to the extra timing margin (e.g., extra delay margin) added to make it more likely that a device in the circuit is going to satisfy specified timing requirements.
As the built-in pessimism of the models is reduced, the reported worst slack for the circuit typically improves. The worst slack is a function of circuit delay and more description of which is provided below. This results in faster time to market and lower timing closure effort. However, improvements in faster time-to market and less design time come at the cost of some loss in yield. Reducing the pessimism may cause a lower yield. Thus, information regarding the relationship between circuit performance (e.g., worst slack) and yield is useful in making decisions on business and design trade-off.
Currently, reduction in model pessimism also requires new libraries that contain performance data (e.g., timing) of the process to be generated. Generating new libraries is time consuming and costly because these new libraries are process-specific and they have to be ordered from foundries and/or library vendors that support the specific process. In particular, when early feedback on timing of the design is needed, it is inconvenient and inefficient to order a new set of libraries.
Moreover, a new set of libraries has to be ordered for each distinct confidence level the circuit designers are interested in. A confidence level can be expressed as a percentage of circuits made using a predetermined fabrication process that meet some predetermined specification. For example, a confidence level of 90% indicates that about 90% of the circuits made using the predetermined fabrication process meet the specification. The percentage of circuits meeting a specification may be referred to as the yield of the circuits. Furthermore, a confidence factor k may be defined to correspond to a given confidence level. For example, k of 3 may represent a confidence level of about 99.87%.
Process variations may be broadly categorized into inter-chip and intra-chip process variations. A chip includes one or more semiconductor circuits fabricated on a piece of silicon. Inter-chip process variations are chip-to-chip variations. The chips may be on the same wafer, such as chip 101 and 103 on wafer 109 shown in FIG. 1A. Alternatively, the chips may be on different wafers, such as chip 131 on wafer 130a and chip 133 on wafer 130b in FIG. 1B. Furthermore, the chips may be in different lots, such as chip 141 in lot 140a and chip 143 on lot 140b in FIG. 1C. Inter-chip process variations are typically modeled by multiple libraries at various process corners, such as best case (BC) 110, typical case (TC) 120 and worst case (WC) 130 libraries, as shown in FIG. 1D.
In contrast, intra-chip process variations are within chip variations. For example, the intra-chip process variation may be demonstrated by measuring performance (e.g., timing) of various components within the same chip. Referring back to FIG. 1A, an exploded view of the chip 103 is shown as the chip 105. Delays through the NAND gates 107a and 107b may be measured to characterize the intra-chip process variation within the chip 105. Intra-chip process variations are usually smaller than inter-chip process variations. Although inter-chip process variation used to dominate process variation, intra-chip process variation starts to become more significant as semiconductor processing technologies enter the sub-micron era. For many sub-micron semiconductor processing technologies (e.g., 90 nm processes), intra-chip variation may affect circuit and/or device matching within a chip.
Intra-chip process variations are typically modeled by different minimum and maximum delays for gates and interconnects on a chip. Conventionally, intra-chip process variations may be specified around each of the inter-chip variation corners of interest, such as shown in FIG. 2 for example. Intra-chip variations may be specified in a number of ways, such as scaling nominal delays, which are calculated at associated inter-chip variation corner, to minimum and maximum values by constants, or using user specified minimum and maximum operating parameters or operating conditions, and scaling factors (also known as k-factors) present in the libraries. Another conventional way to specify intra-chip variations is to use two libraries around each inter-chip variation corner and to calculate minimum delays from one library and maximum delays from the other library.
Conventionally, an early path segment is a series of gates and interconnects for which all delay arcs among the series of gates and interconnects are analyzed at their minimum delay values. A late path segment is a series of gates and interconnects for which all delay arcs among the series of gates and interconnects are analyzed at their maximum delay values. In the current document, the term path is used to describe an early and a late path segment pair that leads to constraint violation at an end point in a circuit. For notational convenience, an early or late path segment is also referred to as an early or late path.
Slack due to setup violation in a circuit is defined by the following equation:Slacksetup=PathDelayearly−PathDelaylate−setup+adj, where PathDelayearly is the sum of minimum delays along early path segment and PathDelaylate is sum of maximum delays along a late path segment. The parameter “adj” includes adjustment for launching and capturing clocks (i.e., period adjustment) as well as other constant pessimism that a user wants to include in timing analysis. Slack due to hold violation may be defined in a similar fashion as follows:Slackhold=PathDelayearly−PathDelaylate−hold+adj. 
If setup and hold values are factored into PathDelaylate, then slack due to either setup or hold violations may be expressed as follows:Slack=PathDelayearly−PathDelaylate+adj  (A).If PathDelayearly and PathDelaylate are expressed as sums of individual arc delays, then equation (A) may be rewritten as follows:Slack=ΣiDelayearly,i−ΣjDelaylate,j+adj  (B),where i and j are indices of the individual delay arc within the path.
Conventionally, static timing analysis assigns minimum and maximum delays to all delay arcs within a path and uses the minimum and maximum delays for analysis of the early and late paths, respectively. For a given end point, however, if early and late paths share a portion of a clock network, then the analysis introduces pessimism equal to the sum of the differences of minimum and maximum arc delays for the shared clock network. The process of removing this pessimism due to overlap in the clock network is commonly referred to as clock path pessimism removal (CPPR).
To aid in the understanding of statistical static timing analysis, a general overview of some statistics principles is provided below. Given n partially correlated, normal random variables X1, X2, . . . Xn, mean and variance of their sum are given as follows:μsum=μX1+μX2+ . . . +μXn  (C);Varsum=r(ΣσXi)2+(1−r)(ΣσXi2)  (D),where μXi and σXi are mean and standard deviation of random variable Xi (1≦i≦n) and r is the correlation coefficient between any pair of variables (0≦r≦1). Furthermore, given partially correlated, normal random variables X and Y, and Z=X−Y, the mean and variance of Z are:μZ=μX−μY  (E);VarZ=(1−r)(σX2+σY2)−r(σX+σY)2  (F),respecitvely,where μX, μY, σX and σY are means and standard deviations of variables X and Y, respectively, and r is their correlation coefficient. The standard deviation of Z is equal to the square root of VarZ.